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-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:08:29 11/25/2012 
-- Design Name: 
-- Module Name:    shrows - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shrows is
port (
	clk : in std_logic;
	datain : in std_logic_vector(127 downto 0);
	dataout : out std_logic_vector(127 downto 0)
);
end shrows;

architecture Behavioral of shrows is


alias a00 : std_logic_vector(7 downto 0) is datain(127 downto 120);
alias a01 : std_logic_vector(7 downto 0) is datain(119 downto 112);
alias a02 : std_logic_vector(7 downto 0) is datain(111 downto 104);
alias a03 : std_logic_vector(7 downto 0) is datain(103 downto 96);

alias a10 : std_logic_vector(7 downto 0) is datain(95 downto 88);
alias a11 : std_logic_vector(7 downto 0) is datain(87 downto 80);
alias a12 : std_logic_vector(7 downto 0) is datain(79 downto 72);
alias a13 : std_logic_vector(7 downto 0) is datain(71 downto 64);

alias a20 : std_logic_vector(7 downto 0) is datain(63 downto 56);
alias a21 : std_logic_vector(7 downto 0) is datain(55 downto 48);
alias a22 : std_logic_vector(7 downto 0) is datain(47 downto 40);
alias a23 : std_logic_vector(7 downto 0) is datain(39 downto 32);

alias a30 : std_logic_vector(7 downto 0) is datain(31 downto 24);
alias a31 : std_logic_vector(7 downto 0) is datain(23 downto 16);
alias a32 : std_logic_vector(7 downto 0) is datain(15 downto 8);
alias a33 : std_logic_vector(7 downto 0) is datain(7 downto 0);


begin


-- wektorek do wklejenia w symulator
-- 482fcd93a97bc09ef6d12aa5b4cf10e1



process (clk)
begin
	if (rising_edge(clk)) then

	dataout <= a00 & a01 & a02 & a03 &
				  a11 & a12 & a13 & a10 &
				  a22 & a23 & a20 & a21 &
				  a33 & a30 & a31 & a32;
	end if;
end process;


end Behavioral;

